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for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim's website at www.maxim-ic.com. general description the max3202e/max3203e/max3204e/max3206e are low-capacitance ?5kv esd-protection diode arrays designed to protect sensitive electronics attached to communication lines. each channel consists of a pair of diodes that steer esd current pulses to v cc or gnd. the max3202e/max3203e/max3204e/max3206e pro- tect against esd pulses up to ?5kv human body model, ?kv contact discharge, and ?5kv air-gap discharge, as specified in iec 61000-4-2. these devices have a 5pf capacitance per channel, making them ideal for use on high-speed data i/o interfaces. the max3202e is a two-channel device intended for usb and usb 2.0 applications. the max3203e is a triple-esd structure intended for usb on-the-go (otg) and video applications. the max3204e is a quad-esd structure designed for ethernet and firewire applications, and the max3206e is a six-channel device designed for cell phone connectors and svga video connections. all devices are available in tiny 4-bump (1.05mm x 1.05mm) ucsp, 6-bump (1.05mm x 1.57mm) ucsp, 9-bump (1.52mm x 1.52mm) ucsp, 6-pin (3mm x 3mm) tdfn, and 12-pin (4mm x 4mm) tqfn packages and are specified for -40? to +85? operation. applications usb video usb 2.0 cell phones ethernet svga video connections firewire features ? high-speed data line esd protection ?5kv?uman body model ?kv?ec 61000-4-2, contact discharge ?5kv?ec 61000-4-2, air-gap discharge ? tiny ucsp package available ? low 5pf input capacitance ? low 1na (max) leakage current ? low 1na supply current ? +0.9v to +5.5v supply voltage range ? 2-, 3-, 4-, or 6-channel devices available max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces ________________________________________________________________ maxim integrated products 1 ordering information 19-2739; rev 3; 12/07 * ucsp reliability is integrally linked to the user? assembly methods, circuit board material, and environment. refer to the ucsp reliability notice in the ucsp reliability section for more information. ** ep = exposed pad. note: all devices operate over -40? to +85? temperature range. + denotes a lead-free package. part pin- package top mark pkg code max3202e ebs-t 4-ucsp* +afv b4-2 m ax 3202e e w s + t 4-ucsp* +aa w41a1-1 max3202eett-t 6-tdfn-ep** +adq t633-2 max3202eebt-t 6-ucsp* +aba b6-4 max3203e ett-t 6-tdfn-ep** +ado t633-2 max3204e ebt-t 6-ucsp* +abb b6-3 max3204eett-t 6-tdfn-ep** +adp t633-2 max3206e ebl-t 9-ucsp* +adu b9-5 max3206eetc 12-tqfn-ep** +aaca t1244-4 selector guide part esd-protected i/o ports max3202eebs-t 2 max3202eews+t 2 max3202eett-t 2 max3203eebt-t 3 max3203eett-t 3 max3204eebt-t 4 max3204eett-t 4 max3206eebl-t 6 max3206eetc 6 pin configurations appear at end of data sheet. firewire is a registered trademark of apple computer, inc. ucsp is a trademark of maxim integrated products, inc. max3202e max3204e max3206e max3208e protected circuit 0.1 f 0.1 f i/0_ i/0 v cc v cc typical operating circuit
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +5v ?%, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5v and t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: limits over temperature are guaranteed by design, not production tested. note 3: idealized clamp voltages (l1 = l2 = l3 = 0) (figure 1 ); see the applications information section for more information. note 4: guaranteed by design. not production tested. v cc to gnd ...........................................................-0.3v to +7.0v i/o_ to gnd ................................................-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70?) 2 2 ucsp (derate 3.0mw/? above +70?) ..............239mw 3 2 ucsp (derate 3.4mw/? above +70?) ..............273mw 3 2 ucsp (derate 3.9mw/? above +70?) ..............308mw 3 3 ucsp (derate 4.7mw/? above +70?) ..............379mw 6-pin tdfn (derate 24.4mw/? above +70?) ..........1951mw 12-pin tqfn (derate 16.9mw/? above +70?) ........1349mw operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? junction temperature .....................................................+150? bump temperature (soldering) (note 1) infrared (15s) ................................................................+220? vapor phase (60s) ........................................................+215? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply voltage v cc 0.9 5.5 v supply current i cc 1 100 na diode forward voltage v f i f = 10ma 0.65 0.95 v positive transients v cc + 25 t a = +25?, ?5kv human body model, i f = 10a negative transients -25 positive transients v cc + 60 t a = +25?, ?kv contact discharge (iec 61000-4-2), i f = 24a negative transients -60 positive transients v cc + 100 channel clamp voltage (note 3) v c t a = +25?, ?5kv air-gap discharge (iec 61000-4-2), i f = 45a negative transients -100 v channel leakage current t a = 0? to +50? (note 4) -1 +1 na channel input capacitance v cc = 5v, bias of v cc /2 5 7 pf esd protection human body model ?5 kv iec 61000-4-2 contact discharge ? kv iec 61000-4-2 air-gap discharge ?5 kv note 1: the ucsp devices are constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board-level solder attach and rework. this limit permits the use of only the solder profiles recommended in the industry-standard specification, jedec 020a, paragraph 7.6, table 3 for ir/vpr and convection reflow. preheating is required. hand or wave soldering is not allowed.
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces _______________________________________________________________________________________ 3 typical operating characteristics (v cc = +5v, t a = +25?, unless otherwise noted.) pin description pin max3202e max3203e max3204e max3206e ucsp tdfn- ep ucsp tdfn- ep ucsp tdfn- ep ucsp tqfn- ep name function a1, b2 3, 6 a1, a2, b3 1, 2, 4 a1, a2, b2, b3 1, 2, 4, 5 a1, a3, b1, b3, c1, c3 1, 2, 3, 7, 8, 9 i/o_ esd-protected channel a2 4 b1 3 b1 3 a2 5 gnd ground b1 1 a3 6 a3 6 c2 11 v cc power-supply input. bypass v cc to gnd with a 0.1? ceramic capacitor. 2, 5 5 4, 6, 10, 12 n.c. no connection. not internally connected. ep exposed pad. connect to gnd. 0.30 0.70 0.50 1.10 0.90 1.30 1.50 clamp voltage vs. dc current max3202e toc01 dc current (ma) clamp voltage (v) 30 70 90 50 110 130 150 1 10 100 1000 25 35 45 55 65 75 85 leakage current vs. temperature max3202e toc02 temperature ( c) leakage current (pa) leakage current per channel 2 4 8 6 10 12 02 1345 input capacitance vs. input voltage max3202e toc03 input voltage (v) input capacitance (pf) v cc = 3.3v v cc = 5.0v
detailed description the max3202e/max3203e/max3204e/max3206e are diode arrays designed to protect sensitive electronics against damage resulting from esd conditions or tran- sient voltages. the low input capacitance makes these devices ideal for high-speed data lines. the max3202e, max3203e, max3204e, and max3206e protect two, three, four, and six channels, respectively. the max3202e/max3203e/max3204e/max3206e are designed to work in conjunction with a device? intrinsic esd protection. the max3202e/max3203e/max3204e/ max3206e limit the excursion of the esd event to below ?5v peak voltage when subjected to the human body model waveform. when subjected to the iec 61000-4-2 waveform, the peak voltage is limited to ?0v when subjected to contact discharge and ?00v when subjected to air-gap discharge. the device that is being protected by the max3202e/max3203e/ max3204e/max3206e must be able to withstand these peak voltages plus any additional voltage generated by the parasitic board. applications information design considerations maximum protection against esd damage results from proper board layout (see the layout recommendations section and figure 2). a good layout reduces the para- sitic series inductance on the ground line, supply line, and protected signal lines. the max3202e/max3203e/max3204e/max3206e esd diodes clamp the voltage on the protected lines during an esd event and shunt the current to gnd or v cc . in an ideal circuit, the clamping voltage, v c , is defined as the forward voltage drop, v f , of the protection diode plus any supply voltage present on the cathode. for positive esd pulses: v c = v cc + v f for negative esd pulses: v c = -v f in reality, the effect of the parasitic series inductance on the lines must also be considered (figure 1). for positive esd pulses: for negative esd pulses: where i esd is the esd current pulse. vv lx di dt lx di dt cfd esd esd () () =? + ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? () 2 13 vv v lx di dt lx di dt cccfd esd esd () () =+ + ? ? ? ? ? ? + ? ? ? ? ? ? () 1 12 max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 4 _______________________________________________________________________________________ l1 protected line l3 d2 ground rail positive supply rail i/o_ d1 l2 figure 1. parasitic series inductance v cc protected line negative esd current pulse path to ground protected circuit gnd d1 i/o_ v c d2 l1 l3 l2 figure 2. layout considerations
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces _______________________________________________________________________________________ 5 during an esd event, the current pulse rises from zero to peak value in nanoseconds (figure 3). for example, in a 15kv iec-61000 air-gap discharge esd event, the pulse current rises to approximately 45a in 1ns (di/dt = 45 x 10 9 ). an inductance of only 10nh adds an additional 450v to the clamp voltage. an inductance of 10nh represents approximately 0.5in of board trace. regardless of the device? specified diode clamp volt- age, a poor layout with parasitic inductance significantly increases the effective clamp voltage at the protected signal line. a low-esr 0.1? capacitor must be used between v cc and gnd. this bypass capacitor absorbs the charge transferred by an +8kv iec-61000 contact discharge esd event. ideally, the supply rail (v cc ) would absorb the charge caused by a positive esd strike without changing its regulated value. in reality, all power supplies have an effective output impedance on their positive rails. if a power supply? effective output impedance is 1 , then by using v = i r, the clamping voltage of v c increas- es by the equation v c = i esd x r out . an +8kv iec 61000-4-2 esd event generates a current spike of 24a, so the clamping voltage increases by v c = 24a 1 , or v c = 24v. again, a poor layout without proper bypassing increases the clamping voltage. a ceramic chip capacitor mounted as close to the max3202e/ max3203e/max3204e/max3206e v cc pin is the best choice for this application. a bypass capacitor should also be placed as close to the protected device as possible. 15kv esd protection esd protection can be tested in various ways; the max3202e/max3203e/max3204e/max3206e are characterized for protection to the following limits: ?5kv using the human body model ?kv using the contact discharge method speci- fied in iec 61000-4-2 ?5kv using the iec 61000-4-2 air-gap discharge method esd test conditions esd performance depends on a number of conditions. contact maxim for a reliability report that documents test setup, methodology, and results. human body model figure 4 shows the human body model, and figure 5 shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of inter- est, which is then discharged into the device through a 1.5k resistor. charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m r d 1.5k high- voltage dc source device under test figure 4. human body esd test model i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 5. human body model current waveform t r = 0.7ns to 1ns 30ns 60ns t 100% 90% 10% i peak i figure 3. iec 61000-4-2 esd generator current waveform
max3202e/max3203e/max3204e/max3206e iec 61000-4-2 the iec 61000-4-2 standard covers esd testing and performance of finished equipment. the max3202e/ max3203e/max3204e/max3206e help users design equipment that meets level 4 of iec 61000-4-2. the main difference between tests done using the human body model and iec 61000-4-2 is higher peak current in iec 61000-4-2. because series resistance is lower in the iec 61000-4-2 esd test model (figure 6) the esd-withstand voltage measured to this standard is generally lower than that measured using the human body model. figure 3 shows the current waveform for the ?kv iec 61000-4-2 level 4 esd contact discharge test. the air-gap discharge test involves approaching the device with a charged probe. the contact discharge method connects the probe to the device before the probe is energized. layout recommendations proper circuit-board layout is critical to suppress esd- induced line transients. the max3202e/max3203e/ max3204e/max3206e clamp to 100v; however, with improper layout, the voltage spike at the device is much higher. a lead inductance of 10nh with a 45a current spike at a dv/dt of 1ns results in an addition- al 450v spike on the protected line. it is essential that the layout of the pc board follows these guidelines: 1) minimize trace length between the connector or input terminal, i/o_, and the protected signal line. 2) use separate planes for power and ground to reduce parasitic inductance and to reduce the impedance to the power rails for shunted esd current. 3) ensure short esd transient return paths to gnd and v cc . 4) minimize conductive power and ground loops. 5) do not place critical signals near the edge of the pc board. 6) bypass v cc to gnd with a low-esr ceramic capac- itor as close to v cc as possible. 7) bypass the supply of the protected device to gnd with a low-esr ceramic capacitor as close to the supply pin as possible. ucsp considerations for general ucsp package information and pc layout considerations, refer to maxim application note 263, wafer-level chip-scale package . ___________________ucsp reliability the ucsp represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. ucsp reliability is integrally linked to the user? assembly meth- ods, circuit-board material, and usage environment. the user should closely review these areas when con- sidering use of a ucsp. performance through operat- ing life test and moisture resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. mechanical stress perfor- mance is a greater consideration for a ucsp. ucsps are attached through direct solder contact to the user? pc board, foregoing the inherent stress relief of a pack- aged product lead frame. solder-joint contact integrity must be considered. table 1 shows the testing done to characterize the ucsp reliability performance. in con- clusion, the ucsp is capable of performing reliably through environmental stresses as indicated by the results in the table. additional usage data and recom- mendations are detailed in the ucsp application note, which can be found on maxim? website at www.maxim-ic.com. chip information process: bicmos low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 6 _______________________________________________________________________________________ charge-current- limit resistor discharge resistance storage capacitor c s 150pf r c 50 to 100 r d 330 high- voltage dc source device under test figure 6. iec 61000-4-2 esd test model
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces _______________________________________________________________________________________ 7 table 1. reliability test data test conditions duration failures per sample size temperature cycle -35? to +85?, -40? to +100? 150 cycles, 900 cycles 0/10, 0/200 operating life t a = +70? 240hr 0/10 moisture resistance -20? to +60?, 90% rh 240hr 0/10 low-temperature storage -20? 240hr 0/10 low-temperature operational -10? 24hr 0/10 solderability 8hr steam age 0/15 esd ?000v, human body model 0/5 high-temperature operating life t j = +150? 168hr 0/45 max3202e v cc gnd i/o1 i/o2 max3203e v cc gnd i/o1 i/o3 i/o2 max3204e v cc gnd i/o1 i/o2 i/o3 i/o4 max3206e v cc gnd i/o1 i/o2 i/o5 i/o6 i/o3 i/o4 functional diagrams
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 8 _______________________________________________________________________________________ 12 n.c. 11 v cc 10 n.c. 45 gnd 6 n.c. 1 2 i/02 3 9 8 7 i/03 i/06 i/05 i/04 max3206e i/01 n.c. tqfn ucsp a2 a3 i/o4 a1 i/o3 i/o2 i/o1 gnd b1 b3 i/o5 c1 c2 c3 i/o6 v cc max3204e ucsp a2 a3 a1 i/o2 i/o3 v cc i/o4 gnd i/o1 b1 b2 b3 max3203e ucsp a2 a3 a1 i/o2 i/o3 v cc gnd i/o1 b1 b3 max3202e ucsp a2 a1 i/o1 gnd top view (bumps on bottom) v cc i/o2 b1 b2 max3206e 1 2 i/02 3 6 5 4 gnd v cc i/04 i/03 i/01 tdfn max3204e 1 2 i/02 3 6 5 4 gnd v cc n.c. i/03 i/01 tdfn max3203e 1 2 n.c. 3 6 5 4 i/01 i/02 n.c. gnd v cc tdfn max3202e ep ep = exposed paddle. connect to gnd. ep ep ep pin configurations
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces _______________________________________________________________________________________ 9 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 4l, ucsp 2x2.eps g 1 1 21-0117 package outline, 2x2 ucsp
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 10 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages . ) 6l, ucsp.eps g 1 1 21-0097 package outline, 3x2 ucsp
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces ______________________________________________________________________________________ 11 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 9lucsp, 3x3.eps package outline, 3x3 ucsp 21-0093 1 1 l
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 12 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 6, 8, &10l, dfn thin.eps
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces ______________________________________________________________________________________ 13 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) common dimensions symbol min. max. a 0.70 0.80 d 2.90 3.10 e 2.90 3.10 a1 0.00 0.05 l 0.20 0.40 pkg. code n d2 e2 e jedec spec b [(n/2)-1] x e package variations 0.25 min. k a2 0.20 ref. 2.00 ref 0.250.05 0.50 bsc 2.300.10 10 t1033-1 2.40 ref 0.200.05 - - - - 0.40 bsc 1.700.10 2.300.10 14 t1433-1 1.500.10 mo229 / weed-3 0.40 bsc - - - - 0.200.05 2.40 ref t1433-2 14 2.300.10 1.700.10 t633-2 6 1.500.10 2.300.10 0.95 bsc mo229 / weea 0.400.05 1.90 ref t833-2 8 1.500.10 2.300.10 0.65 bsc mo229 / weec 0.300.05 1.95 ref t833-3 8 1.500.10 2.300.10 0.65 bsc mo229 / weec 0.300.05 1.95 ref 2.300.10 mo229 / weed-3 2.00 ref 0.250.05 0.50 bsc 1.500.10 10 t1033-2
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces 14 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 24l qfn thin.eps
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces ______________________________________________________________________________________ 15 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max3202e/max3203e/max3204e/max3206e low-capacitance, 2/3/4/6-channel, 15kv esd protection arrays for high-speed data interfaces maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 _____________________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 3 12/07 added 3202eews+t tdfn and tqfn packages, updated package information 1, 2, 3, 4, 6, 8, 12?5

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